DocumentCode
418531
Title
Glitching power reduction through supply voltage adaptation mechanism for low power array structure design
Author
Hong, Sangjin ; Chin, Shu-Shin ; Sadasivam, Magesh
Author_Institution
Dept. of Electr. & Comput. Eng., Stony Brook Univ., NY, USA
Volume
2
fYear
2004
fDate
23-26 May 2004
Abstract
A novel supply voltage switching mechanism for reducing power dissipation of array structures is presented. With this mechanism, the supply voltage levels are successively activated by external clock signal in the direction of signal propagation. The mechanism eliminates power dissipated by the glitches while the speed of the array structure can be maintained. The mechanism is easily incorporated so that no circuit change in the existing array structure is required.
Keywords
array signal processing; integrated circuit design; logic arrays; logic circuits; logic design; switching; external clock signal; glitching power reduction; integrated circuit design; logic design; low power array structure design; power dissipation; signal propagation direction; supply voltage adaptation mechanism; supply voltage switching mechanism; Adaptive arrays; Clocks; Delay; Logic; Pipelines; Power dissipation; Power supplies; Registers; Switches; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN
0-7803-8251-X
Type
conf
DOI
10.1109/ISCAS.2004.1329376
Filename
1329376
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