Modelling and implementation of twisted differential on-chip interconnects for crosstalk noise reduction

A simple generic interconnect architecture is presented to allow effective cancellation of inductive and capacitive noise in high-speed on-chip interconnect lines. The approach is based on the principle of constructing periodically twisted differential line pairs for parallel interconnect segments in order to eliminate the mutual coupling influences. Detailed simulations show that the twisted-differential lines (TDL) provide high-speed and crosstalk-immune interconnects, compared to single-ended and differential lines.