BDD circuit optimization for path delay fault testability

The complexity of integrated circuits is rapidly growing. This leads to more and more time and money spent on the test of these circuits. Besides minimizing the logic needed for a given function the testability of the resulting circuit becomes a major issue during synthesis. One way to synthesize a circuit for a given function is to directly convert the binary decision diagram (BDD) of that function into a circuit. It is known that optimizations of the BDD transfer to the derived circuit. Therefore in this paper we evaluate different optimization techniques for BDDs based on variable reordering with respect to the path delay fault testability of the resulting circuit. We show an optimization strategy that allows to compromise during synthesis between logic size and testability.