Exact algorithms for coupling capacitance minimization by adding one metal layer

Due to the rapid development of manufacturing process technology and tight marketing schedules, chip design and manufacturing always work towards an integrated solution to achieve an enhanced product for fast time-to-market and higher niche profit. For high-end "high-volume" products, one good option for further improving chip performance is to add extra metal layers based on an existing design after all easy circuit fixes and process tricks have been applied. This strategy has been applied by the main integrated device manufacturers. In contrast to most low volume ASIC, the additional metal layer cost is low due to cost averaging over huge volumes. We address the NLM (new layer migration) problem which eliminates coupling capacitance violations for speed push in a given routing solution by migrating some wire segments to a metal layer newly inserted under the commonly used metal filling post process for manufacturability and coupling control. We first propose an exact linear-time algorithm to judge whether a feasible solution exists or not. Then we present a provably optimal algorithm to eliminate as many coupling violations as possible. At the same time, the total coupling capacitance on both metal layers is minimized. For n wire segments, the time complexity of the algorithm is O(n³2/log(n)). Finally, an LP approach is presented as post processing to adjust segment positions when the two layers have layer-dependent design spacing rules.