Symbol-spaced delay circuit design with half-rate clock timing for multi-taps FIR filter as pre-emphasis

Author

Li, Miao ; Kwasniewski, Tad ; Noel, Peter

Author_Institution

Dept. of Electron., Carleton Univ., Ottawa, Ont.

Volume

1

fYear

2004

fDate

6-9 Dec. 2004

Firstpage

337

Abstract

A FIR filter for pre-emphasis has been used to counteract inter-symbol interference (ISI) in high-speed backplane data transmission. A novel circuit design for retiming data using a half-rate clock for the taps of a FIR filter is proposed. HSPICE simulation results for CMOS 0.18 mum technology verify that the jitter of PRBS15 (2¹⁵ - 1) data at rate of 6.25 Gbps with a pre-emphasis value of 50% can be reduced to approximately 14 psec and thereby alleviating the requirement on clock frequency

Keywords

CMOS integrated circuits; FIR filters; SPICE; data communication; delay circuits; intersymbol interference; jitter; 0.18 micron; CMOS technology; HSPICE simulation; PRBS15 jitter; backplane data transmission; data retiming; half-rate clock timing; intersymbol interference; multitap FIR filter; preemphasis; symbol-spaced delay circuit design; Backplanes; CMOS technology; Circuit simulation; Circuit synthesis; Clocks; Data communication; Delay; Finite impulse response filter; Intersymbol interference; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on

Conference_Location

Tainan

Print_ISBN

0-7803-8660-4

Type

conf

DOI

10.1109/APCCAS.2004.1412763

Filename

1412763