VLSI architecture design for variable-size block motion estimation in MPEG-4 AVC/H.264

Author

Wei, Cao ; Gang, Mao Zhi ; Qiang, Lv Zhi ; Zhang Yan

Author_Institution

Microelectron. Center, Harbin Inst. of Technol., China

Volume

1

fYear

2004

fDate

6-9 Dec. 2004

Firstpage

617

Abstract

VBSME is adopted in the MPEG-4 AVC/H.264 standard. In this paper, we proposed a new VLSI architecture for VBSME with FS and TSS algorithms to support two resolutions. The architecture can reuse the smaller blocks´ SADs to calculate 4.1 motion vectors of a 16 × 16 block in parallel. Our design was implemented with 0.25μm CMOS technology. Under a clock frequency of 150Mhz, the architecture allows the real-time processing of 352 × 288 (or 720 × 576) at 30fps with FS (or TSS) in a search range [-16, +15].

Keywords

CMOS digital integrated circuits; VLSI; digital signal processing chips; motion estimation; parallel architectures; telecommunication standards; video coding; 0.25 micron; 150 MHz; CMOS; MPEG-4 AVC/H264 standard; VLSI architecture; motion vectors; real-time processing; variable-size block motion estimation; Automatic voltage control; CMOS technology; Clocks; Computer architecture; Frequency; MPEG 4 Standard; Microelectronics; Motion estimation; Registers; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on

Print_ISBN

0-7803-8660-4

Type

conf

DOI

10.1109/APCCAS.2004.1412838

Filename

1412838