IMD sweet-spot control on junction FET devices using a gate bias resistor

In this paper, the use ofa gate hias resistor is proposed for conforming a wide linearity sweet-spot in class B or C amplifiers based on junction FET technologies. An illustrative E-pHEMT transistor has been characterized in terms of its intermodulation distortion (UMD) behaviour versus input power, paying particular attention to the evolution of the gate-to-source voltage where the sweet-spot appears. The DC current, resulting from rectification of large gate-to-source voltage swings, has also been studied. It proved to he useful as au element for dynamically adjusting VGs with the RF power level, through the addition of an adequate resistor in the DC path. Finally, experimental results of this sweet-spot enhancement in both B and C amplifying classes are shown, either using the classical twotone excitation or a real QPSK modulated signal.