Memory hierarchy usage estimation for global loop transformations

Major parts of the power dissipation for data dominated embedded system is due to huge amounts of data transfers to and from large consuming data memories. Global loop transformations play a crucial role in optimizing the memory accesses. By improving regularity and temporal locality of these memory accesses using loop transformations, data can be potentially stored closer to the datapath in smaller less power consuming memories. To steer the selection of which loop transformations to perform, high level memory estimation is used. In state of the art memory estimation techniques the mapping of data to different parts of the memory hierarchy are not considered since these decisions are made in later system design phases. However, estimates of these mapping decisions is crucial, since they greatly influence the consequences of different transformations. In this paper we propose a systematic methodology for hierarchical memory usage estimation which considers also future data mapping decisions for a memory hierarchy. The goal of the estimation is to evaluate global loop transformation decisions for different platforms and keep only the optimal decision (in terms of energy) for each platform. We demonstrate our methodology on a real- life multimedia video coder (QSD PCM) which shows that for 1k layer one memory, a factor of 2 improvement in total energy can be achieved.