DocumentCode
435921
Title
Modeling the effects of patterning error on MOSFET
Author
Pun, C.H. ; Lai, P.T. ; Wong, A.K.K.
Author_Institution
Dept. of Electr. & Electron. Eng., Hong Kong Univ., China
Volume
2
fYear
2004
fDate
18-21 Oct. 2004
Firstpage
1049
Abstract
During IC fabrication, layout shapes do not exactly replicate onto wafers due to distortions in pattern-transfer processes. Conformal mapping is used to give a simple model to estimate the effect of the distortion on the I-V characteristics of MOSFETs. The method is verified by the device simulator DA VINCI. The impact of pattern distortion of MOSFET on circuit performance is also examined by the proposed model.
Keywords
MOSFET; circuit simulation; integrated circuit layout; integrated circuit modelling; ternary semiconductors; DA VINCI; I-V characteristics; IC fabrication; MOSFET; circuit performance; conformal mapping; pattern distortion; pattern-transfer process; patterning error; Charge carrier processes; Circuit optimization; Circuit simulation; Conformal mapping; MOSFET circuits; Poisson equations; Semiconductor device modeling; Shape; Tiles; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on
Print_ISBN
0-7803-8511-X
Type
conf
DOI
10.1109/ICSICT.2004.1436686
Filename
1436686
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