A digital square-law compander

Square-law compression and expansion of signals are widely used in telecommunications to improve the signal-to-noise ratio (SNR). In conventional bipolar components, multipliers are used to perform automatic gain control. Complete monolithic implementation of such companders is impossible because of the large size of resistors and capacitors required to implement shifting and averaging. This paper describes an alternative circuit, which is based on delta-sigma modulation. We propose a fully digital scheme based on non-linear arithmetic operations on a delta-sigma pulse density stream. A square-law compressor of the form √ x and a square-law expander circuit of the form x² are simulated and evaluated.