MOSFET optimization in deep submicron technology for charge amplifiers

Author

De Geronimo, Gianluigi ; O´Connor, Paul

Author_Institution

Div. of Instrum., Brookhaven Nat. Lab., Upton, NY, USA

Volume

1

fYear

2004

fDate

16-22 Oct. 2004

Firstpage

25

Abstract

The optimization of the input MOSFET for charge amplifiers in deep submicron technologies is discussed. After a review of the traditional approach, the impact of properly modeling the equivalent series noise and gate capacitance of the MOSFET is presented. It is shown that the minimum channel length and the maximum available power are not always the best choice in terms of resolution. Also, in an optimized front-end, the low frequency noise contribution to the equivalent noise charge may depend on the time constant of the filter. As an example, results from the commercial TSMC 0.25 μm CMOS technology are reported.

Keywords

CMOS integrated circuits; MOSFET; amplifiers; integrated circuit noise; nuclear electronics; 0.25 mum; MOSFET gate capacitance; MOSFET series noise; charge amplifiers; commercial TSMC CMOS technology; deep submicron technology; equivalent noise charge; filter time constant; input MOSFET optimization; low frequency noise contribution; minimum channel length; optimized front-end; CMOS technology; Current density; Design optimization; Equations; Filters; Low-frequency noise; MOSFET circuits; Parasitic capacitance; Sensor phenomena and characterization; Signal resolution;

fLanguage

English

Publisher

ieee

Conference_Titel

Nuclear Science Symposium Conference Record, 2004 IEEE

ISSN

1082-3654

Print_ISBN

0-7803-8700-7

Electronic_ISBN

1082-3654

Type

conf

DOI

10.1109/NSSMIC.2004.1462062

Filename

1462062