System-level communication modeling for network-on-chip synthesis

As we are entering the network-on-chip era and system communication is becoming a dominating factor, communication abstraction and synthesis are becoming the integral part of system design flows. The key to the success of any design flow are well defined abstraction levels and models, which enable automation of early validation, synthesis and verification. In this paper, we define system communication abstraction layers and corresponding design models that support successive, stepwise refinement from abstract message passing down to a cycle accurate, bus-functional implementation. Experimental results show the benefits of our definitions and design flow.