A 10-bit 20-Msample/s sub-ranging ADC for low-power and low-voltage applications

For the development of new low-voltage, low-power imaging microsystems, we have designed a 10-bit 20 Msample/s ADC. It is a 3-stage sub-ranging architecture with rail-to-rail dynamic input range. To achieve low-voltage and low-power operation, transistor-level design for building blocks such as op-amps and flash ADCs was required. Complementary CMOS comparators with no static consumption were used to build a new low-power 4-bit flash ADC with rail-to-rail input range. A novel 1.7 volts minimal supply voltage, 120 dB op-amp structure was designed. To reach 20-MHz sampling rate, the ADC makes use of time-interleaving, switched capacitor amplifiers, which perform dynamic frequency compensation for speed optimisation and offset cancellation. This ADC has been fabricated and tested and will be integrated on one chip including colour image sensors in a BICMOS process. A 20-Msample/s rate has been obtained with a supply voltage down to 2.4 volts and 60mW power consumption (Vdd=3 volts).