A CMOS 12-bit 15 Msample/s digitally self-calibrated pipelined A/D converter

In this paper design techniques for low-power high-resolution A/D conversion are presented. It is shown that the accuracy is determined primarily by the input sampling capacitance. Therefore in a low-power design some kind of calibration is needed to obtain a high resolution. Here digital self-calibration is employed. By combining opamp sharing with capacitor scaling, only the load of the first stage contributes significantly to the overall power budget. In order to also reduce the capacitive loading of the first stage, the input signal range must be extended. This is achieved by adding extra comparators at the input stage. An experimental prototype in 0.8µm CMOS was designed for a 5 Volt supply. Measured results at 15 MS/s are a S/(N+THD) of 69dB with 110 mW power drain. All spurs are below -80 dB. With reduced bias-currents similar behaviour is maintained upto 10 MS/s at 60 mW.