Low power self-timed floating-point divider in 0.25um technology

This paper describes a low power self-timed radix-2 56-b floating-point divider based on redundant signed digit arithmetic. By introducting static circuits in the noncritical data path, power consumption can be decreased by 46% without performance degradation compared to a fully dynamic dual-rail implementation. The proposed divider was fabricated using a 5-metal 0.25µm standard CMOS process. The measured results show 43.5ns worst-case delay and 35mA operating current with a 2.5V supply.