A 10-bit 200 MS/s CMOS parallel pipeline A/D converter

A 10-bit 200 MS/s parallel pipeline ADC is presented. It consists of a front-end sample-and-hold circuit and four parallel pipelined component ADCs followed by a digital offset compensation. By incorporating double sampling both in the S/H circuit and the component ADCs a power dissipation of only 280 mW from a 3.0 V supply is achieved. The circuit is implemented with a standard 0.5 µm CMOS process occupying 7.4 mm². According to the measurements, a DNL and INL of 0.8 LSB and 0.9 LSB, respectively, is achieved while the peak SFDR is 56 dB with a 200 MS/s sample rate.