• DocumentCode
    439568
  • Title

    A 2 GHz Δ Σ fractional-N frequency synthesizer in 0.35 µm CMOS

  • Author

    Ahola, R. ; Halonen, K.

  • Author_Institution
    Helsinki University of Technology, Espoo, Finland
  • fYear
    2000
  • fDate
    19-21 Sept. 2000
  • Firstpage
    472
  • Lastpage
    475
  • Abstract
    A 2 GHz fractional-N frequency synthesizer for telecommunications applications is presented. The synthesizer includes a multiple-modulus CMOS prescaler capable of operating at input frequencies of up to 2.15 GHz with a power dissipation of 12.5 mW, a third-order MASH ΔΣ-modulator that controls the modulus of the prescaler, and a phase detector and chargepump that doesn´t suffer from dead-zone problems. The synthesizer achieves a close-in phase noise of-79 dBc/Hz while dissipating only 22.6 mW from a 2.7 V supply. The synthesizer has been implemented in a 0.35 µm CMOS technology.
  • Keywords
    Bandwidth; Frequency conversion; Frequency synthesizers; Multi-stage noise shaping; Noise shaping; Phase locked loops; Phase noise; Quantization; Read only memory; Voltage-controlled oscillators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2000. ESSCIRC '00. Proceedings of the 26rd European
  • Conference_Location
    Stockholm, Sweden
  • Type

    conf

  • Filename
    1471312