• DocumentCode
    439623
  • Title

    High-speed CMOS analog Viterbi detector for 4-PAM partial response signalling

  • Author

    Zand, Bahram ; Johns, David A.

  • Author_Institution
    University of Toronto, Toronto, Canada
  • fYear
    2001
  • fDate
    18-20 Sept. 2001
  • Firstpage
    229
  • Lastpage
    232
  • Abstract
    A high-speed analog Viterbi detector based on 4-PAM duobinary scheme is designed and implemented in a 0.25 µm CMOS process. This chip is the first analog integrated implementation of a reduced state sequence detector. Due to test equipment limitations, experimental results are given for 200 Mb/s operation while simulation results indicate a speed of 1 Gb/s. Power dissipation is 60 mW from a 2.5V supply.
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2001. ESSCIRC 2001. Proceedings of the 27th European
  • Conference_Location
    Villach, Austria
  • Type

    conf

  • Filename
    1471375
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=439623