Design of clock generating fully integrated PLL using low frequency reference signal

Systems including for example micromechanical oscillators can provide a frequency reference, which can be in the order of few kilohertz. This paper describes a design procedure for a fully integrated charge pump phase locked loop (PLL), which can utilise low reference frequencies. Noise is taken into account in the design process and simulated example of a PLL is presented. Presented theory allows the design of a fully integrated PLL in favour of either noise or power consumption.