DocumentCode
440456
Title
Hybrid genetic algorithm engine for high-speed floorplanning
Author
Yoshikawa, Masaya ; Terai, Hidekazu
Author_Institution
Dept. of VLSI Syst. Design, Univ. Ritsumeikan, Kyoto, Japan
Volume
1
fYear
2005
fDate
28 Aug.-2 Sept. 2005
Abstract
This paper discusses the architecture for high-speed floorplanning using sequence pair representation based on hybrid genetic algorithms. The hybrid optimization of GA and SA in the proposed architecture realized searching not only globally but also locally. To keep general purpose, the proposed architecture is flexible for many genetic operations on GA and achieves high speed processing by adopting dedicated hardware. Furthermore, the proposed architecture realized not only the pipeline on evaluation phase, but also the pipeline on evolutionary phase on GA. Simulation results evaluating the proposed architecture are shown to the effectiveness.
Keywords
VLSI; circuit optimisation; genetic algorithms; integrated circuit layout; dedicated hardware; evaluation phase; evolutionary phase; high speed processing; high-speed floorplanning; hybrid genetic algorithm engine; sequence pair representation; Computer architecture; Engines; Genetic algorithms; Hardware; Optimization methods; Pipelines; Sampling methods; Search methods; Simulated annealing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuit Theory and Design, 2005. Proceedings of the 2005 European Conference on
Print_ISBN
0-7803-9066-0
Type
conf
DOI
10.1109/ECCTD.2005.1522942
Filename
1522942
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