Load-balanced CICB packet switch with support for long round-trip times

Combined input-crosspoint buffered (CICB) packet switches relax arbitration timing and provide high-performance switching. However, the amount of memory in buffered crossbars required to achieve 100% throughput under flows with high data rates is proportional to the number of ports, N, and the crosspoint buffer size k, which is defined by the distance between the line cards and the buffered crossbar. Long distances between the line cards and the buffered crossbar can make a CICB switch costly to implement. In this paper, we propose a load-balanced CICB packet switch to support long distances between the buffered crossbar and the line cards using crosspoint buffers of small size. The proposed switch reduces the required crosspoint buffer size by a factor of N and keeps the cells in sequence.