Time-multiplexing of signal using highly integrated digital delay: an FPGA implementation

We have designed and implemented on a Xilinx SpartanIIE FPGA a highly integrated time-multiplexing device by means of using multiple fixed delays. Signals coming from MWPCs (multi wire proportional chambers) front end readout circuitry can be multiplexed in time using selected delay values. Up to 5 channels can be merged into one using delays in increments of 150 ns. As a consequence, usage of one multi-hit channel to measure timing of 5 channels is possible. Inside the FPGA a 36 to 8 multiplexing is performed, resulting in a reduction, of more than a factor of four, of the number of multi-hit TDC channels needed.