DocumentCode
451910
Title
Estimating Architectural Resources and Performance for High-Level Synthesis Applications
Author
Sharms, A. ; Jain, Rajiv
Author_Institution
Department of Electrical and Computer Engineering, University of Wisconsin, Madison, WI
fYear
1993
fDate
14-18 June 1993
Firstpage
355
Lastpage
360
Abstract
In this paper we present a solution to the following problems related to architectural synthesis. Given an input specification and a perfomance constraint, determine a lower bound number of resources (active and interconnect) required to execute the data flow graph while satisfying the performance constraint. Conversely, determine a lower bound performance for executing an input specification for a given number of resources (active and interconnect). The generated bounds are close to the actual designs synthesized by several existing systems.
Keywords
Algorithm design and analysis; Application software; Character generation; Clocks; Delay estimation; Flow graphs; High level synthesis; Pipeline processing; Process design;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1993. 30th Conference on
ISSN
0738-100X
Print_ISBN
0-89791-577-1
Type
conf
DOI
10.1109/DAC.1993.203974
Filename
1600247
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