Comparative Design Validation Based on Event Pattern Mappings

This paper proposes a new methodology for performing comparative validation between two specifications of a system at different levels of abstraction. The methodology consists of two steps : extracting a high-level simulation from a low-level simulation by recursively recognizing and naming patterns of events, and compare the extracted simulation to a high-level simulation. This paper introduces a new semantics for high-level simulation (partial order with duration events), describes a new algorithm to compare an extracted simulation (total order with duration events) and a high-level simulation, and lists performance results of the comparison algorithm.