Resolving Signal Correlations for Estimating Maximum Currents in CMOS Combinational Circuits

Currents flowing in the power and ground (P&G) lines of CMOS digital circuits affect both circuit reliability and performance by causing excessive voltage drops. Maximum current estimates are therefore needed in the P&G lines to determine the severity of the voltage drop problems and to properly design the supply lines to eliminate these problems. These currents, however, depend on the specific input patterns that are applied to the circuit. Since it is prohibitively expensive to enumerate all possible inputs, this problem has, for a long time, remained largely unsolved. In [1], we proposed a pattern-independent, linear time algorithm (iMax) that estimates an upper bound envelope of all possible current waveforms that result from the application of different input patterns to the circuit. While the bound produced by iMax is fairly tight on many circuits, there can be a significant loss in accuracy due to correlations between signals internal to the circuit. In this paper, we present a new partial input enumeration (PIE) algorithm to resolve these correlations and significantly improve the upper bound (in one case, reducing the error by 64% on a circuit with about 1,700 gates). We also show good speed performance, analyzing circuits with more than 20,000 gates in about 2 hours on a SUN ELC. We demonstrate with extensive experimental results that the algorithm represents a good time-accuracy trade-off and is applicable to large VLSI circuits.