Evaluating Coverage of Error Detection Logic for Soft Errors using Formal Methods

Author

Krautz, U. ; Pflanz, M. ; Jacobi, C. ; Tast, H.W. ; Weber, K. ; Vierhaus, H.T.

Author_Institution

Kaiserslautern Univ.

Volume

1

fYear

2006

fDate

6-10 March 2006

Firstpage

1

Lastpage

6

Abstract

In this paper we describe a methodology to measure exactly the quality of fault-tolerant designs by combining fault-injection in high level design (HLD) descriptions with a formal verification approach. We utilize BDD based symbolic simulation to determine the coverage of online error-detection and -correction logic. We describe an easily portable approach, which can be applied to a wide variety of multi-GHz industrial designs

Keywords

binary decision diagrams; error correction; error detection; fault tolerance; formal verification; high level synthesis; binary decision diagrams; error correction logic; error detection logic; fault-tolerant designs; formal methods; formal verification; high level design descriptions; soft error injection; Binary decision diagrams; Circuit faults; Circuit simulation; Computer errors; Electrical fault detection; Error correction; Fault detection; Hardware; Logic; Radiation detectors; Error Detection and Correction; Fault/Error Coverage; Formal Verification; Soft Error Injection;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe, 2006. DATE '06. Proceedings

Conference_Location

Munich

Print_ISBN

3-9810801-1-4

Type

conf

DOI

10.1109/DATE.2006.244062

Filename

1656872