Design and Implementation Of Word-Level Embedded Block Coding Architecture in JPEG 2000 Decoder

Author

Chang, Yu-Wei ; Fang, Hung-Chi ; Chen, Chun-Chia ; Chen, Liang-Gee

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ.

Volume

2

fYear

2006

fDate

14-19 May 2006

Abstract

This paper presents a word-level decoding architecture of embedded block coding (EBC) in JPEG 2000. This architecture decodes one coefficient per cycle based on the proposed word-level decoding algorithm. This algorithm eliminates state variable memories by decoding all bit-planes in parallel. The proposed column-switching scan order overcomes intra bit-plane dependency and inter bit-plane dependency to enable parallel processing. Implementation results show the proposed architecture can decode 54 MSamples/s at 54 MHz, which can support HDTV 720 p (1280times720, 4:2:2) decoding at 30 frames/sec in real time

Keywords

block codes; decoding; image coding; JPEG 2000 decoder; column-switching scan order; decoding; parallel processing; word-level embedded block coding architecture; Arithmetic; Block codes; Computer architecture; Decoding; Digital signal processing; Discrete wavelet transforms; Parallel processing; Scalability; Streaming media; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech and Signal Processing, 2006. ICASSP 2006 Proceedings. 2006 IEEE International Conference on

Conference_Location

Toulouse

ISSN

1520-6149

Print_ISBN

1-4244-0469-X

Type

conf

DOI

10.1109/ICASSP.2006.1660376

Filename

1660376