PATARA: Solid-State Neutron Detector Readout Electronics with Pole-Zero and Complex Shaping and Gated Baseline Restorer for the SNS

A prototype neutron detector array has been developed for the Spallation Neutron Source (SNS). The High Efficiency Neutron Detector Array (HENDA) will be the highest spatial resolution neutron detecting linear array available anywhere. The front-end electronics have been developed on a prototype chip, Patara, from a TSMC 0.35-micron fabrication. The Patara chip is a 16-channel preamp/shaper/blr for high-efficiency solid-state neutron detectors. It features a regulated cascode preamplifier with adjustable gain, digitally adjustable leakage current compensation and active feedback reset network with matching pole/zero cancellation network, and an input pulse polarity adjustment. The shaper has a five-pole semi-Gaussian response utilizing two pairs of current-input complex-conjugate poles with gated baseline restoration. The system dissipates 3.7 mW/channel. Measurements indicate an overall gain of 9.7 mV/fC and 5.65 mV/fC for full- and half-gain settings, 270 nanosecond full-width half-maximum (FWHM) output, and 550 RMS electrons input noise for a 5 pF detector capacitance.