Delay and Clock Skew Variation due to Coupling Capacitance and Inductance

With aggressive scaling of technology, and corresponding increase of circuit density interconnect has become the most critical factors that influence timing characteristics of integrated circuits performance. This is due to increasing length and aspect ratio of interconnect lines leading to growing capacitive and inductive coupling. In this paper, the effects of capacitive and inductive coupling on delay uncertainty and clock skew have been analyzed. The analysis and the simulation results show that coupling capacitance and mutual inductance have opposite impacts on delay and clock skew variations. It is illustrated that while capacitive coupling worsens both variations, growing inductive coupling can actually counter-balance the negative impacts to some degree.