Efficient Message Passing Architecture for High Throughput LDPC Decoder

Author

Cui, Zhiqiang ; Wang, Zhongfeng

Author_Institution

Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR

fYear

2007

fDate

27-30 May 2007

Firstpage

917

Lastpage

920

Abstract

In this paper, we propose an efficient message passing architecture for permutation matrices based LDPC code decoders. Min-sum algorithm is reformulated to facilitate significant reduction of routing complexity and memory usage. For a (2048, 1723) (6, 32) LDPC code with 4-bit quantization, 54% outgoing wires per variable node unit and 90% outgoing wires per check node unit can be saved. To further reduce hardware complexity, an optimized nonuniform quantization scheme using only 3 bits to represent each message has been investigated. The simulation result shows that it has only 0.25dB performance loss from the floating-point SPA

Keywords

matrix algebra; message passing; parity check codes; quantisation (signal); 3 bit; 4 bit; LDPC code; high throughput LDPC decoder; message passing; min-sum algorithm; optimized nonuniform quantization; permutation matrices; reduced hardware complexity; Computer architecture; Decoding; Hardware; Message passing; Parity check codes; Performance loss; Quantization; Routing; Throughput; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on

Conference_Location

New Orleans, LA

Print_ISBN

1-4244-0920-9

Electronic_ISBN

1-4244-0921-7

Type

conf

DOI

10.1109/ISCAS.2007.378075

Filename

4252785