DocumentCode
464801
Title
High performance processor array for image processing
Author
Foldesy, Peter ; Zarándy, Ákos ; Rekeczky, Csaba ; Roska, Tamás
Author_Institution
Comput. & Autom. Res. Inst., Hungarian Acad. of Sci., Budapest
fYear
2007
fDate
27-30 May 2007
Firstpage
1177
Lastpage
1180
Abstract
The ASIC implementation of a digital cellular visual microprocessor architecture is introduced. The processor array is constructed of simple, locally interconnected 8 bit microprocessors, operating in an extended SIMD mode. The processor array can be equipped with on-chip photo diode array, using 3D integration technology
Keywords
image processing; microprocessor chips; parallel processing; photodiodes; 3D integration technology; ASIC implementation; SIMD mode; digital cellular visual microprocessor architecture; high performance processor array; image processing; on-chip photo diode array; Analog computers; Arithmetic; Filters; High performance computing; Image processing; Morphology; Pixel; Sensor arrays; Silicon; Xenon;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
Conference_Location
New Orleans, LA
Print_ISBN
1-4244-0920-9
Electronic_ISBN
1-4244-0921-7
Type
conf
DOI
10.1109/ISCAS.2007.378260
Filename
4252850
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