A Low Jitter CMOS PLL Clock Synthesizer with 20-400 MHz Locking Range

This paper describes the design of a CMOS PLL clock synthesizer targeting biomedical applications in the 20-400 MHz range. Based on integer-N architecture, the synthesizer produces a 400-mV LVDS output signal swing on a 1.2 V common mode level under 50-Omega load. Fabricated in a 0.35-mum N-well CMOS process technology, the PLL achieves a period jitter of 6.5-ps_rms and 38-ps_pp at 216 MHz with a phase noise of -120 dBc/Hz at frequency offsets above 10 KHz. The phase noise response has a peak of -115 dBc/Hz at the loop bandwidth.