Process and Temperature Calibration of PLLs with BiST Capabilities

This paper presents two self-calibrating charge pump phase locked loop (CP-PLL) architectures, the first utilizing a ring VCO (voltage controlled oscillator) and the second implemented using a LC-tank VCO. Each design utilizes frequency-modulated analog-to-digital converter(s) (FM ADCs) as part of a calibration circuit to compensate for process and temperature (PT) variations. For the ring VCO-based PLL, compensation is achieved over all four process corners and for temperatures of 0degC, 27degC, and 60degC by dynamically modifying the charge-pump current. In the LC-tank VCO-based PLL design, the tuning range of the VCO is tuned according to the detected process shift. Each FM ADC consumes only 729muWof power for the worst-case scenario and 0.0016mm² of area. For the two 0.18mum CMOS PLL case studies investigated here, calibration is achieved for non-ideal operating environments.