Test Generation in the Presence of Timing Exceptions and Constraints

Generating test patterns without considering timing exceptions and constraints can lead to invalid test responses, resulting in false failures on the tester or yield loss. A path-oriented approach to handle timing exception paths with setup violations during at-speed test generation has been presented in (V. Vorisek et al., 2006). This paper presents a unified and complete algorithm for computing test responses in the presence of timing exceptions with both setup and hold violations, and Boolean timing constraints. The new algorithm analyzes all possible effects of glitches in the circuit. It resolves pessimism in the case of multiple interacting timing exception paths. The new method significantly reduces the number of unknowns in the test responses, resulting in improved test coverage and test compression. The new method can be applied to 1) any fault model, 2) any test pattern, 3) any simulation environment, and/or 4) any test generator.