Energy-Aware Differential Current Sensing for Global On-Chip Interconnects

Global on-chip interconnects in 70 nm and beyond present challenges in satisfying delay constraints while minimizing energy consumption, especially energy due to leakage [1]. Although many global interconnects may have low activity factors (e.g. cache fill bus) thus reducing dynamic power, leakage is still a great concern. Leakage is an increasing concern in traditional repeated interconnects due to the large device sizes required to meet tight delay constraints [2] and the inherently distributed nature of the repeaters which complicates power gating. Differential current sensing has been demonstrated to have advantages in speed, dynamic power and layout simplicity, however static and leakage power remain a weakness [3]. This paper presents an improved differential current sense amplifier, called differential leakage-aware sense amplifier(DLASA), with power gating that results in 39.6% reduced leakage and static power compared to conventional differential current sensing. When compared with high Vt repeaters the proposed sense amplifier reduces leakage by 41%. Finally, this current sensing approach results in faster interconnects with less overall energy than high Vt repeaters for 1 to 10 mm wire. The new circuit technique can also be applied for leakage reduction in other differential circuits and in the presence of increased static.