A New Memory-Based Systolic Algorithm for DST with Low Hardware Complexity

In this paper a new memory-based VLSI algorithm for 1D-DST is proposed. This algorithm uses a new formulation of the DST into cyclic convolution forms that uses a new input restructuring sequence. This approach significantly reduces the overheads necessary to restructure the DST into cyclic convolution structures. We can further use this appropriate reformulation of the DST to map it onto a linear systolic array with high through-put and low I/O cost. The systolic array that can be obtained has a high degree of modularity and regularity with only local interconnections.