DocumentCode
472761
Title
Verification of an Analytic Model for Latchup in Epitaxial CMOS
Author
Chatterjee, A. ; Seitchik, J.A. ; Chern, J.H. ; Yang, P. ; Wei, C.C.
Author_Institution
Semiconductor Process and Design Center, Texas Instruments, Inc. MS 369, P.O. Box 655621. Dallas. Tx 75265
fYear
1987
fDate
22-23 May 1987
Firstpage
83
Lastpage
84
Abstract
This paper presents 2D simulation and experimental results for direct verification of an analytic model for the holding voltage in epitaxial CMOS that emphasized the role of conductivity modulation. Improvement in the holding voltage with lower doping in the anode and cathode regions, as predicted by the model, is compared with simulation results. The key concept of the model is the equivalence of a 2D thyristor to a p-i-n diode of the same geometry. This paper verifies this concept. Simulated as well as experimentally determined I-V characteristics of thyristors are compared with those of p-i-n diodes.
Keywords
Analytical models; Anodes; Conductivity; Doping; P-i-n diodes; Predictive models; Semiconductor device modeling; Semiconductor process modeling; Thyristors; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 1987. Digest of Technical Papers. Symposium on
Conference_Location
Karuizawa, Japan
Type
conf
Filename
4480433
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