Leveraging sequential equivalence checking to enable system-level to RTL flows

It has long been the practice to create models in C or C+ + for architectural studies, software prototyping and RTL verification in the design of Systems-on-Chip (SoC). It is often the case that by the end of a design project, multiple C models exist for different uses. Since a lot of time is invested in ensuring the functional correctness of these models via their use in system-level simulations, they often become "golden " functional reference models. Design teams are moving towards leveraging these system-level models to reduce the time needed for design and verification of RTL On the design side, the use of high-level synthesis tools to synthesize RTL from C/C+ + models is gaining ground for certain classes of blocks within a design. On the verification front, temporal differences at interfaces and in internal states between system-level models and RTL prevent the use of combinational equivalence checkers. This paper focuses on the use of sequential equivalence checking to verify functional equivalence between system-level models and RTL and describes the challenges and vale of using it in system-level to RTL flows.