Development of pipeline ADC for the luminosity detector at ILC

The design and measurement results of the prototype 1.5-bit stages developed for a 10 bit pipeline ADC for the luminosity detector (LumiCal) at International Linear Collider (ILC) are discussed. The motivation for the chosen architecture is presented and followed by the description of core analog blocks in a 1.5-bit stage pipeline ADC. The prototype stages were designed and fabricated in 0.35 μm CMOS technology. Wide spectrum of measurements of static (INL, DNL) and dynamic (SFDR, SNHR, SINAD, THD) parameters performed to understand and quantify the circuit performance is presented. Single 1.5-bit stage operation is studied in detail.