DocumentCode
47810
Title
An Analytical Threshold Voltage Model for Triple-Material Cylindrical Gate-All-Around (TM-CGAA) MOSFETs
Author
Dubey, Souvik ; Santra, Aparna ; Saramekala, Gopikrishna ; Kumar, Manoj ; Tiwari, P.K.
Author_Institution
Dept. of Electron. Eng., Indian Inst. of Technol., Varanasi, Varanasi, India
Volume
12
Issue
5
fYear
2013
fDate
Sept. 2013
Firstpage
766
Lastpage
774
Abstract
In this paper, an analytical threshold voltage model is proposed for a triple-material cylindrical gate-all-around MOSFET considering parabolic approximation of the potential along the radial axis. The center (axial) and the surface potential models are obtained by solving the 2-D Poisson´s equation in the cylindrical coordinate system. This paper refutes the estimation of the natural length using surface potential as in previous work and proposes the use of center-potential-based natural length formulation for an accurate subthreshold analysis. The developed center potential model is used further to formulate the threshold voltage model and also extract drain-induced barrier lowering (DIBL) from the same. The effects of the device parameters like the cylinder diameter, oxide thickness, gate length ratio, etc., on the threshold voltage and DIBL are also studied in this paper. The model is verified by the simulations obtained from 3D numerical device simulator Sentaurus from Synopsys.
Keywords
MOSFET; Poisson equation; numerical analysis; semiconductor device models; 2D Poisson equation; 3D numerical device simulator Sentaurus; DIBL; TM-CGAA MOSFET; analytical threshold voltage model; axial potential model; center potential model; center-potential-based natural length formulation; cylinder diameter; cylindrical coordinate system; device parameters; drain-induced barrier lowering; gate length ratio; natural length; oxide thickness; parabolic approximation; radial axis; subthreshold analysis; surface potential model; triple-material cylindrical gate-all-around MOSFET; Electric potential; Logic gates; MOSFET; Numerical models; Semiconductor device modeling; Silicon; Threshold voltage; Center potential; drain induced barrier lowering (DIBL); hot carrier effect (HCE); short-channel effects (SCEs);
fLanguage
English
Journal_Title
Nanotechnology, IEEE Transactions on
Publisher
ieee
ISSN
1536-125X
Type
jour
DOI
10.1109/TNANO.2013.2273805
Filename
6562818
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