Optimized Design of Interconnected Bus on Chip for Low Power

Author

Li, Donghai ; Ma, Guangsheng ; Feng, Gang

Author_Institution

Coll. of Comput. Sci. & Technol., Harbin Eng. Univ.

Volume

2

fYear

2006

fDate

20-24 June 2006

Firstpage

298

Lastpage

302

Abstract

In this paper, we firstly propose an on-chip bus power consumption model, which includes the self transition power dissipated on the signal lines and the coupled transition power dissipated between every two signal lines. And then a new heuristic algorithm is proposed to determine a physical order of signal lines in bus. Experimental results show that average power saving is 26.85%

Keywords

energy conservation; integrated circuit design; integrated circuit interconnections; logic design; power consumption; system buses; system-on-chip; coupled transition power dissipation; heuristic algorithm; interconnected bus on chip design optimization; on-chip bus power consumption model; power saving; self transition power dissipation; Clocks; Coupling circuits; Design optimization; Educational institutions; Energy consumption; Hardware; Heuristic algorithms; Integrated circuit interconnections; Power system interconnection; Very large scale integration; coupled; interconnected bus; power optimization; self transition; transition;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer and Computational Sciences, 2006. IMSCCS '06. First International Multi-Symposiums on

Conference_Location

Hanzhou, Zhejiang

Print_ISBN

0-7695-2581-4

Type

conf

DOI

10.1109/IMSCCS.2006.247

Filename

4673720