A SystemC-Based Transaction Level Modeling of On-Chip-Bus

As the rapid development of semiconductor technology, more and more processor cores and large reusable components have been integrated on a single silicon die. And the rapid increase of requirement from applications is leading to the exploration of SOC.On-chip-bus is a key part of SOC.A SystemC-based Transaction Level Modeling of on-chip-bus is introduced in this paper. As an example, the DVB-C is described in detail. Experiments demonstrated that this model can work well. And the time bottleneck of current hardware/software co-design method can be eased effectively. This model can improve efficiency and reduce the cost of products.