Effect of flip-chip package parameters on CDM discharge

Author

Karp, James ; Kireev, Vassili ; Tsaggaris, Dean ; Fakhruddin, Mohammed

Author_Institution

Xilinx Inc., San Jose, CA

fYear

2008

fDate

7-11 Sept. 2008

Firstpage

1

Lastpage

5

Abstract

CDM peak currents (I_peak) were studied for the same I/O pin on different dies and flip-chip packages. It is found that I_peak has strong correlation with linear function of two capacitances: die-to-lid capacitance (C_DUT) and C_DUT normalized per die area (C_DUT/A). The proposed physical model relates CDM current to the two competing discharge paths. The local path is from Si-substrate, where the charge collected from a few millimeters radius. This part of I_peak is a function of C_DUT/A. The global path is through a package ground plane, where the charge is collected from Si-substrate via metal routing to the taps. This part of I_peak is a function of C_DUT.

Keywords

capacitance; discharges (electric); elemental semiconductors; flip-chip devices; integrated circuit packaging; silicon; CDM discharge; Si; die-lid capacitance; flip-chip package; metal routing; package ground plane; Capacitance; Clocks; Drives; Flip-flops; Logic; Oscilloscopes; Packaging; Routing; Tiles; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Overstress/Electrostatic Discharge Symposium, 2008. EOS/ESD 2008. 30th

Conference_Location

Tucson, AZ

Print_ISBN

978-1-58537-146-4

Electronic_ISBN

978-1-58537-147-1

Type

conf

Filename

4772108