DocumentCode
483351
Title
Potential barrier based clamp: A new device structure for low voltage triggering
Author
Bobde, Madhur ; Mallikarjunaswamy, Shekar ; Ho, Moses ; Hébert, François
Author_Institution
Alpha & Omega Semicond., Sunnyvale, CA
fYear
2008
fDate
7-11 Sept. 2008
Firstpage
83
Lastpage
87
Abstract
This paper presents a flexible low voltage trigger structure based on a pinched-off JFET potential barrier. It has low leakage, low trigger voltage that can be controlled by the gate, and does not require high doping levels. In this work, the proposed JFET has been used to trigger a vertical NPN transistor to create a low voltage transient voltage suppressor. The fabricated low voltage TVS has low leakage and low capacitance loading and excellent clamping at high current.
Keywords
electrostatic discharge; flexible electronics; junction gate field effect transistors; semiconductor device breakdown; transients; trigger circuits; capacitance loading; doping levels; flexible low-voltage trigger structure; leakage voltage; low-voltage transient voltage suppressor; pinched-off JFET; potential barrier-based clamp; vertical NPN transistor; Capacitance; Clamps; Doping; Electrostatic discharge; Leakage current; Low voltage; Protection; Semiconductor diodes; Thyristors; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Overstress/Electrostatic Discharge Symposium, 2008. EOS/ESD 2008. 30th
Conference_Location
Tucson, AZ
Print_ISBN
978-1-58537-146-4
Electronic_ISBN
978-1-58537-147-1
Type
conf
Filename
4772118
Link To Document