DocumentCode
483352
Title
A scalable compact model of interconnects self-heating in CMOS technology
Author
Manouvrier, Jean-Robert ; Fonteneau, Pascal ; Legrand, Charles-Alexandre ; Richier, Corinne ; Beckrich-Ros, Hélène
Author_Institution
STMicroelectron., Crolles
fYear
2008
fDate
7-11 Sept. 2008
Firstpage
88
Lastpage
93
Abstract
High Joule heating during ESD transient is a major cause of failure in metal interconnects. In order to provide a realistic assessment of current and future interconnect performance, a scalable compact model of self heating in isolated metal lines, valid in the ESD time range (time < 100 ns), has been developed. This model turns out to be in very good agreement experimental results, and it can be used to forecast TLP I(V) characteristics of isolated metal wires.
Keywords
CMOS integrated circuits; electrostatic discharge; integrated circuit interconnections; CMOS; ESD transient; Joule heating; interconnects; isolated metal lines; scalable compact model; self-heating; CMOS technology; Capacitance; Dielectric materials; Electrostatic discharge; Heating; Predictive models; Semiconductor device modeling; Temperature; Thermal conductivity; Thermal resistance;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Overstress/Electrostatic Discharge Symposium, 2008. EOS/ESD 2008. 30th
Conference_Location
Tucson, AZ
Print_ISBN
978-1-58537-146-4
Electronic_ISBN
978-1-58537-147-1
Type
conf
Filename
4772119
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