Optimized implementation of a parallel DSP architecture for real time stacked beam radar signal processing

This paper presents a parallel processing architecture, based on four TMS320C44 VME-bus DSP boards, for real time implementation of six clutter map constant false alarm rate (CM-CFAR) detectors together with a height finding extractor. The latter is based on a centroidal interpolation of the angular location of the target. The optimal processing speed has been achieved by fully exploiting the capacity of the ´C44 processor. The implemented configuration is well adapted for two dimension stacked beam surveillance radar. The overall parallel processing scheme interconnections and the real time implementation results are presented and discussed.