Multi-codec variable length decoder design with configurable processor

Multi-codec video decoder is widely used with increasing number of video standards. Although this trend requires flexible system design that can accommodate various standards, most Variable Length Decoders (VLDs) for video applications have been designed with the ASIC approach because of the poor performance of software implementation on a processor. This paper presents a design concept for a flexible VLD using configurable processor with additional custom instructions for acceleration. The simulation result shows that the proposed approach improves the performance by 4.68 ~ 5.59 times compared to that of a general purpose processor, enabling MPEG-4 SD video sequence to be decoded in real time on the processor. Our design is flexible in that any VLD process for various video standards can be executed on it without hardware modification.