An all-digital phase-locked loop with fast acquisition and low jitter

An all-digital phase-locked loop that achieves fast acquisition and low jitter was developed for high-speed clock generation. By employing a time-to-digital converter (TDC), the frequency difference is precisely measured and converted to the control word of the digital oscillator. Using this feature, the ADPLL has a faster lock-in time than previous digital phaselocked loops. The ADPLL was implemented using a 0.9 V 32 nm practical transistor model (PTM). The simulation results show that the proposed ADPLL achieves 5 and 10 reference cycles of frequency and phase acquisitions at 700 MHz with peak to peak jitter < 53 ps.