Modeling functional unit delays for bit-level chaining

The functional units used for high-level synthesis are typically modeled to have fixed delays once the input slew rate and the out loading are given. However, if two or more functional units are chained, then the total delay may not be the same as the sum of the individual delays. In this paper, we present a new approach to modeling the timing of functional units such that the delay can be calculated efficiently and accurately even with bit-level chaining. For this, we analyze each functional unit used for high-level synthesis to obtain pin-to-pin delays, classify them according to the delay variation, and calculate the total delay of chained functional units based on the classification. We present the efficiency and accuracy of the proposed approach through experiments with various combinations of functional units.