A simple background interstage gain calibration technique for pipeline ADCs

The pipelined architecture is one of the most popular analog-to-digital converter (ADC) architectures. Various circuit nonidealities such as finite opamp gain and mismatch in capacitors limit the pipelined ADC´s performance. In this paper, a new technique for the calibration of interstage gain errors in pipelined ADC´s are described. The proposed calibration scheme uses a slow but accurate ADC as a reference ADC to determine the gain error of the stage under calibration in digital domain independent other stages. Then, correction of each stage error is done in analog domain. The calibration technique calibrates capacitor mismatch as well as finite opamp dc gain, while the digital redundancy compensates for comparator offset. Simulation shows that with this calibration scheme, SNDR improved from 39 dB to 72 dB for a 12-bit pipeline ADC.